Oracle CPU-56T Instrukcja Użytkownika Pobierz pdf (Strona 76)

Devices’ Features and Data Paths Interrupt Controller

76 SPARC/CPU−56T

Interrupt Controller

The UltraSPARC−IIi+ provides a 6−bit wide interrupt vector for 63 interrupt sources.a

The UPA interrupt concentrator (UIC) provides the inputs for all necessary interrupts. It

monitors all interrupts using a round−robin scheme with 33 MHz, converts them to a

device−own vector and transmits this vector to the processor. The PCI interrupts engine

(PIE) reflects every vector in one state bit. From the state bit a new vector is generated and

transmitted to the processor′s execution unit. If more than one interrupt state bit is active,

the transmitting sequence of the new interrupt vector is priority controlled.a

Every interrupt routed to the interrupt controller can be enabled or disabled separately in

the interrupt source and in the processor.

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Oracle CPU-56T Instrukcja Użytkownika Strona 76