Oracle CPU-56T Instrukcja Użytkownika Pobierz pdf (Strona 89)

Introduction OpenBoot Firmware

SPARC/CPU−56T 89

Additionally, CORE is designed to reach the following goals:

S Ability to use I/O devices including serial port, flash, floppy, and net early on the cold

boot sequence of a firmware client.a

S Basic system tests that can replace existing POST in min. mode.

S System testing may be done using the POST drop−in in max. mode.

S Error recovery from exceptions which currently do not exist in OpenBoot and from

any fatal conditions during flash update

S Developing standard validation test suites that could prevent major bugs in CORE

and clients

S Sample client codes that could facilitate any client porting

CORE Workflow

The following figure describes the workflow of CORE.

Power−On Switch

Control+P

user−interface

<diag−switch?>

<diag−level>

Control+U

If no activity

detected for 10 sec.

bPOST

cPOST

(Client)

Client

CORE

User Interface

YES

TRUE

FALSE

MAX

TRUE

FALSE

MIN

1 2 ... 84 85 86 87 88 89 90 91 92 93 94 ... 144 145

Brak uwag

Oracle CPU-56T Instrukcja Użytkownika Strona 89